1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing same. More specifically, the present invention relates to a MNOS (metal nitride oxide semiconductor) or a MONOS (metal oxide nitride oxide semiconductor) nonvolatile semiconductor memory device, which is capable of storing information by utilizing electric charge that is trapped by an insulating film of a multi-layer structure thereof, and a method for manufacturing same.
2. Description of the Related Art
Floating gate (FG) transistors are generally employed for memory devices of the nonvolatile semiconductor memory device, which is also referred to flash memory. The FG transistor is a type of a device having a dual-layer gate electrode structure, in which information electric charge is stored within a first gate electrode that functions as a floating gate electrode. In this structure, the first gate electrode is formed on a silicon oxide film disposed on a principal surface of a semiconductor substrate in a floating manner, and an interlayer insulating film comprising a combined structure of a silicon oxide film and a silicon nitride film is disposed on the upper surface of the first gate electrode, and further a second gate electrode, which also functions as a control electrode, is formed on the upper surface of the interlayer insulating film.
However, the principle of the retention of the information electric charge in the FG transistor provides poor characteristics of the retention of the information electric charge, so that a relatively thicker silicon oxide film having a thickness of 9 nm or more is required for a tunnel oxide film disposed between the principal surface of the semiconductor substrate and the floating gate electrode. This configuration adversely limit an effort for reducing of the electric voltage required for writing and erasing the information electric charge.
Thus, MNOS transistors or MONOS transistors comprising a multi-layer film of a silicon oxide film and a silicon nitride film have been employed in recent years. Since the MNOS transistor is capable of accumulating information electric charge within the gate insulating films of the dual layer-structure at an interface state created in an interface region between each of the dual insulating films or at an electric charge trapping state created within the insulating film, the reduction of the thickness of the tunnel oxide film between the principal surface of the semiconductor substrate and the floating gate electrode can be easily achieved, and therefore the thinner tunnel oxide film having a thickness of 3 nm or less can be employed. Therefore, MNOS transistor possibly provides, in principle, to reduce the operating electric voltage, and in particular, the voltage for writing and erasing the information electric charge.
In operating the MNOS transistor, the writing of the information electric charge is conducted by directly injecting electron from the semiconductor substrate to the above-mentioned interface region through a tunnel of a silicon oxide film having a thickness of about 2 nm that is formed on the principal surface of the semiconductor substrate, and conversely, the erasing of the information electric charge is conducted by releasing the electric charge from the interface region to the semiconductor substrate. The writing state of the information electric charge corresponds to a logic “1” for stored information, and the erasing state of the information electric charge corresponds to a logic “0” for stored information. Thus, various studies have intensively been carried out for practically utilizing the M(O)NOS transistors, which are principally capable of writing and erasing thereof at lower voltage, for the application of the memory devices of the nonvolatile semiconductor memory devices such as flash memory.
The exemplary application of the MONOS transistors for the nonvolatile semiconductor memory device of the flash memory is a memory device, a fundamental structure of which is disclosed in U.S. Pat. No. 5,768,192. Further, more recently, a technology useful for considerably simplifying the manufacturing process for forming the nonvolatile memory is disclosed in U.S. Pat. No. 5,966,603 as a disclosure of NROM (nitride read only memory). In this disclosure, the fundamental structure of the nonvolatile memory device is similar to that disclosed in U.S. Pat. No. 5,768,192.
A conventional method for manufacturing NROM will be described below with reference to FIGS. 9A to 9E. FIGS. 9A to 9E are the cross sectional views of the NROM cut along the word line, showing the processing steps thereof.
As shown in FIG. 9A, a surface of a silicon substrate 1 is thermally oxidized to form a silicon oxide film, and then a silicon nitride film is deposited thereon via chemical vapor deposition (CVD), and thereafter the surface of the deposited silicon nitride film is oxidized via an ordinary thermal oxidization or radial oxidization to transform the surface of the silicon nitride into a silicon oxide film. Thus, an ONO films 3 comprising a triple-layer structure of the silicon oxide film/silicon nitride film/silicon oxide film is formed.
Then, as shown in FIG. 9B, a patterned resist layer 6 having a stripe shaped (slit shaped) diffusion layer-pattern is formed on the ONO films 3 via a known lithography technology. Then, the exposed portion of the ONO films 3 is etched via the etching mask of the patterned resist layer 6 by a known etching technology.
Then, as shown in FIG. 9C, n-type impurity such as arsenic is implanted through the ion implantation mask of the patterned resist layer 6 as, and thereafter the patterned resist layer 6 is removed.
Then, as shown in FIG. 9D, entire surface thereof is thermally oxidized. An insulating film having a thickness of about 110 nm is formed on a diffusion layer 2 via the thermal oxidization process to form a bit-line oxide 13.
Then, as shown in FIG. 9E, a polysilicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are successively deposited to form an electrical conducting layer 14, and thereafter the electrical conducting layer is processed via a known lithography method and a known dry etching method to form a word line.
A bit line of the NROM cell, which is formed of the diffusion layer 2, is formed on the silicon substrate 1 via the above-mentioned manufacturing method, and the ONO films 3 provides a region for writing and erasing the information electric charge. Further, the word line is formed perpendicularly to the bit line to complete a fundamental structure of the NROM cell.
Next, the basic operation of the MONOS transistor, which forms the fundamental structure of the above-mentioned NROM cell, will be described below. In the operation of writing the information electric charge (electron in this example), as shown in FIG. 10A for example, the silicon substrate 1 and the first diffusion layer 2a are set at the ground potential, the voltage VW of the second diffusion layer 2b is set at 3 V, and the voltage VGW of the gate electrode 15 is set at about 5 V. When these voltages are applied thereto, a flow of electron (channel electric current) is created from the first diffusion layer 2a, which functions as the source, to the second diffusion layer 2b, which functions as the drain, and the channel electric currents become channel hot electrons (CHE) in vicinity of the second diffusion layer 2b, and some of the generated channel hot electrons flow beyond the barrier of the silicon oxide film (first insulating film 3a) that underlies the ONO films 3, and are trapped by the trapping region 17 of the silicon nitride film (second insulating film 3b). Thus, when the writing operation of electrons is conducted, the information electric charge is stored in the region of the silicon nitride film near the edge of the second diffusion layer 2b. 
Then, in the operation of reading the information, the second diffusion layer 2b, on the other hand, is set to the ground potential to function as the source as shown in FIG. 10B, and a voltage VR of the first diffusion layer 2a, which functions as the drain, is set to 1.5 V, and a voltage VGR of the gate electrode 15 is set to about 3 V. Here, the silicon substrate 1 is maintained to the ground potential. Having this configuration, when the logic state is “1” indicating that electrons are written into the trapping region 17, no current flows between the first diffusion layer 2a and the second diffusion layer 2b. On the contrary, when the logic state is “0” indicating that no electron is written into the trapping region 17, electric current flows between the first diffusion layer 2a and the second diffusion layer 2b. As such, the written information is read.
Then, in the operation of erasing the information, the configuration shown in FIG. 10A, for example, includes that the silicon substrate 1 and the first diffusion layer 2a are set to the ground potential, and a voltage VE of the second diffusion layer 2b is set at 5 V, and the voltage VGE of the gate electrode 15 is set at about −5 V. When these voltages are applied thereto, holes, which are created by the band-to-band tunneling (BTBT) due to the band-bending generated in a region of the edge of the second diffusion layer 2b where the edge overlaps the gate electrode, are introduced into the above-mentioned trapping region 17, thereby erasing the written information.
In this erasing operation, the holes created by the BTBT are pushed out toward the channel region, and accelerated when the holes proceed through a depletion layer of pn junction created between the p-type channel region and the n-type diffusion layer 2 to become the higher-energy state. The level of the acceleration of the holes depends on the state of the depletion layer of the pn junction, i.e., voltage between the drain and the substrate. If there is no factor for drawing the created holes toward the side of the gate electrode 15 (e.g., negative charge, or negative gate voltage), the holes proceed outside to create the substrate electric current.
In the case of the MONOS cell, when the MONOS cell is in the state in which the writing operation is completed, clusters of electrons appear in the silicon nitride film (second insulating film 3b) in vicinity of the drain, and the above-mentioned holes form electric flux lines toward the cluster of electrons and are exerted with a force along thereof. Thus, the holes acquire the higher energy state so that the energized holes are capable of exceeding the energy barrier of Si/SiO2, and the energized holes are injected into the inside of the silicon nitride film where the injected holes are recombined with electrons. When the recombination phenomenon proceeds, the number of electrons trapped in the silicon nitride film decreases and the number of the electric flux lines from the holes to the electrons decreases, and thus the driving force for injecting the holes into the ONO films 3 also decreases. Consequently, the MONOS cells utilizing the above-mentioned writing and erasing scheme does not have theoretical bases for causing the over-erasing problem, which often becomes problem for the operation of ordinary FG cell.
Nevertheless, the above-mentioned conventional MNOS or MONOS nonvolatile semiconductor memory device may cause another problem, in which an inroad portion called as “bird's beak”, which is formed by the growth of the oxide film in the lateral direction, is created during the above-mentioned formation of the bit-line oxide 13 via thermal oxidization. The growth of the bird's beak reduces the distance between each of the diffusion layers (for example, between the first diffusion layer 2a and the second diffusion layer 2b), thereby easily causing the shortcutting of the channel therebetween. This limits the miniaturization of the NROM cell, constraining the manufacturing of the NROM having higher-density or higher-integration.
Further, in the conventional method, a bending of the ONO films 3 near the edge of the bit-line oxide 13 due to the creation of the bird's beak alters the band structure of the silicon nitride film, deteriorating the characteristics of maintaining the information electric charge. In addition, since various processing steps such as the formation of the patterned resist layer, the stripping thereof and the thermal oxidization thereof are carried out after the formation of the ONO films 3 and before the formation of the electrical conductive layer 14 thereon for the word line, it is difficult to maintain better interface characteristics between the word line and the ONO films 3, thereby deteriorating the reliability of the formed devices.